Behavioral v/s Structural Programming in VHDL

VHDL :

       VHSIC Hardware Description Language.It was developed by IBM,Texas Instrumentation and Intermetrics in  1983. It is a language to describe digital Electronics System. It is used for designing Simulation and Synthesis of any Chip. This language has been standaralized by IEEE in 1987.
 

Behavioral Modeling : 

            In this type of modelling specifies the behavior of an entity are as a set of statements that are executed sequentially in specified order. the programmer must write  the appropriate code in a sequence of there occurrence . 

VHDL program illustrating a behavioral modeling 

library ieee;

    use ieee.std_logic_1164.all;

entity half_adder is

    port(x,y: in std_logic;

        sum,carry : out std_logic);

    end half_adder;  

    

    architecture adder_half of half_adder is

begin 

   sum<= x AND y;

   carry<=x XOR y;

  

 end adder_half;

Structural Modelling:

      In structural Modelling tan entity is described as a set of interconnected components . In the below example two components dipesh_xor and dipesh_and is used to carry out a half adder .

VHDL program illustrating Sequential Modelling:

library ieee;

    use ieee.std_logic_1164.all;

entity half_adder is

    port(x,y: in std_logic;

        sum,carry : out std_logic);

    end half_adder;  

    

    architecture adder_half of half_adder is

        component dipesh_xor

            port(a,b: in std_logic;

                c: out std_logic); 

            end component;

            

        component dipesh_and

            port(a,b: in std_logic;

                c:out std_logic);

        end component;

        

        begin x1: dipesh_xor port map(x,y,sum);

            x2: dipesh_and port map(x,y,carry);

        end adder_half;